The present invention relates to a booster circuit used for a flash memory or the like.
Generally, to write/erase data in/from a flash memory, channel hot electrons or a tunnel current is used. For this purpose, a high voltage is required because a high electric field must be applied to the gate. Conventionally, a terminal for supplying a high external voltage is arranged independently of the power supply terminal. In recent years, however, a single power supply is used to simplify the external power supply circuit. The power supply voltage to be supplied is conventionally often 5 V, though it is lowering to 2 or 3 V to reduce the power consumption or increase the operation speed. The memory chip incorporates a booster circuit for generating a voltage higher than the externally supplied power supply voltage, and recently, the boosting ratio need be higher than the conventional one.
FIG. 16 shows a booster circuit disclosed in Japanese Patent Laid-Open No. 9-8229 (to be referred to as prior art 1 hereinafter). This booster circuit comprises diodes D1 to D5, capacitors CP1 to CP4, a capacitive load CL, and driving circuits DV1 and DV2.
Referring to FIG. 16, a circuit constituted by, e.g., the diode D2 and the capacitor CP2 is called a pump circuit PC. The booster circuit shown in FIG. 16 has four pump circuits PC. Nodes between the diodes D1 to D4 and the one-terminal sides of the capacitors CP1 to CP4 are represented by N1 to N4, respectively; a node between the diode D5 and the load capacitor CL, NL; and nodes between the capacitors CP1 and CP2 and the output terminals of the driving circuits DV1 and DV2, N181 and N182, respectively.
Connection in the booster circuit shown in FIG. 16 will be described next. The anode side of the diode D1 is connected to the power supply, and the cathode side is connected to the capacitor CP1 through the node N1 to form the first pump circuit. The anode side of the diode D2 is connected to the node N1, and the cathode side is connected to the capacitor CP2 through the node N2 to constitute the second pump circuit. In a similar manner, a plurality of pump circuits, i.e., the third and fourth pump circuits respectively constituted by the diodes D3 and D4 and the capacitors CP3 and CP4 are connected in series.
The other terminal of each of the odd-numbered capacitors CP1 and CP3 counted from the first pump circuit is connected to the driving node N181. The other terminal of each of the even-numbered capacitors CP2 and CP4 counted from the first pump circuit is connected to the driving node N182.
A two-phase clock signal .phi.181 and a clock .phi.182 as the inverted signal of the clock .phi.181, which have timings as shown in FIGS. 17A and 17B, are supplied to the outputs, i.e., the driving nodes N181 and N182 of the driving circuits DV1 and DV2, respectively. The driving nodes N181 and N182 for the capacitors CP1 and CP3 and the capacitors CP2 and CP4 are alternately driven in opposite phases, thereby outputting a high voltage from an output terminal Voz. In the arrangement shown in FIG. 16, a voltage five times higher than a power supply voltage Vcc is obtained. Note that the capacitor CP is called a pump capacitance.
The operation of this circuit will be described next in more detail with reference to FIGS. 16, 17A, and 17B.
For the descriptive convenience, assume that the circuit is constituted by two pump circuits, the load capacitor CL is connected to the node N3, the power supply voltage Vcc is 4 V, the capacitors CP1 and CP2 have the same capacitance value as that of the load capacitor CL, the threshold value of the diodes D1 to D3 is 0 V, and low and high levels of the clocks .phi.181 and .phi.182 are 0 V and 4 V, respectively.
In the initial state at time T180, the driving nodes N181 and N182 are at 0 V, and the nodes N1, N2, and NL are at 4 V because the power supply voltage Vcc is supplied through the diodes D1 to D3. As a result, the output voltage Voz is also 4 V.
At time T181, the clock .phi.181 rises to set the driving node N181 at 4 V. The voltage at the node N1 temporarily changes from 4 V to 8 V and immediately stabilizes at 5.3 V because charges flow to the nodes N2 and NL through the diodes D2 and D3. This is because charges accumulated in the capacitor CP1 are distributed to the capacitor CP2 and the load capacitor CL.
The clock .phi.182 does not change, and the driving node N182 also maintains 0 V.
At time T182, the clock .phi.181 falls to set the driving node N181 at 0 V. Charges stored on the N181 side of the capacitor CP1, which correspond to 4 V, are removed through the driving circuit DV1.
Simultaneously, the voltage on the node N1 side of the capacitor CP1 lowers from 5.3 V to 1.3 V and then rises to 4 V because of supply of the power supply voltage Vcc through the diode D1. Letting C (F) be the electrostatic capacitance of the capacitor CP1, the loss charge amount due to this discharge is given by C.times.Vcc (coulomb).
On the other hand, the clock .phi.182 rises to set the driving node N182 at 4 V. The voltage on the node N2 side of the capacitor CP2 temporarily becomes 9.3 V because 4 V is added to 5.3 V. However, since the diode D3 is turned on to transfer charges to the load capacitor CL, the node N2 side stabilizes at 7.3 V, and the output voltage Voz also becomes 7.3 V.
At time T183, the clock .phi.181 rises again to repeat the same operation as at time T181.
On the other hand, when the clock .phi.182 falls, the driving node N182 is set at 0 V, and charges stored on the driving node N182 side of the capacitor CP2 are removed through the driving circuit DV2. Letting C (F) be the electrostatic capacitance of the capacitor CP2, the loss charge amount due to this discharge is given by C.times.Vcc (coulomb).
This boost operation is repeated, and the output terminal Voz finally converges to 12 V. Since discharge is performed twice in one period, the loss charge amount for one period is C.times.Vcc.times.2 (coulomb). Since Vcc is 4 V, the loss charge amount is 8C (coulomb).
In prior art 1, letting Z be the number of pump circuits, the boost voltage is generally given by (Z+1).times.Vcc, and the loss charge amount is given by Z.times.C.times.Vcc (coulomb). Therefore, the loss charge amount per unit boost ratio is represented by {Z/(Z+1)}.times.C.times.Vcc (coulomb).
FIG. 18 shows another conventional booster circuit (to be referred to as second prior art hereinafter) disclosed in "1996 Symposium on VLSI Circuits Digest of Technical Papers", pp. 110-111. FIG. 18 shows the circuit in mode 2. This booster circuit is of a full-wave rectification type and aims at increasing the current amount to be output from the booster circuit and reducing the power consumption by recycling some removed charges.
The booster circuit of prior art 2 comprises PMOS transistors M1 and M4, NMOS transistors M2, M3, M5, M6, M7, and M8, drivers DV201 and DV202 for inverting an input signal and outputting the inverted signal, diodes D201 and D202, and capacitors C201 to C204. Nodes between the transistors M1 and M2, between the transistors M2 and M3, between the transistors M5 and M7, and between the transistors M6 and M8 are represented by N201, N202, N203 and N205, respectively.
The connection relationship in the circuit of prior art 2 shown in FIG. 18 will be described.
A clock .phi.201 is connected to the gate of the transistor M2 and to the gate of the transistor M4 through the driver DV202. A clock .phi.202 is connected to the gate of the transistor M3 and to the gate of the transistor M1 through the driver DV201.
The source of the transistor M1 is connected to a power supply Vcc while the drain is connected to the drains of the transistors M2 and M4 and the capacitor C201 at the node N201. The source of the transistor M3 is connected to ground GND while the drain is connected to the sources of the transistors M2 and M4 and the capacitor C202 at the node N202.
Each of the nodes N203 and N204, i.e., the other terminal of each of the capacitors C201 and C202, is connected to the source of the corresponding one of the transistors M5 and M6 and the drain of the corresponding one of the transistors M7 and M8. The drains of the transistors M5 and M6 and the anodes of the diodes D201 and D202 are connected to the power supply Vcc. The cathode of the diode D201 is connected to the gates of the transistors M5 and M8 and the capacitor C203. The cathode of the diode D202 is connected to the gates of the transistors M6 and M7 and the capacitor C204. The other terminal of each of the capacitors C203 and C204 is connected to the corresponding one of clocks .phi.203 and .phi.204. The sources of the transistors M7 and M8 are connected to a load capacitor CL at a node NL.
The operation of prior art 2 will be described next with reference to the timing charts of FIGS. 19A to 19H.
For the descriptive convenience, in FIGS. 19A to 19H, assume that the power supply voltage Vcc is 4 V, and the capacitors C201 and C202 have the same capacitance value C (F) as that of the load capacitor CL. In addition, the threshold value of the transistors M1 to M8 is 0 V, and low and high levels of the clocks .phi.201 to .phi.204 are 0 V and 4 V, respectively.
The clocks .phi.201 to .phi.204 have the same frequency. The clock signals .phi.201 and .phi.202 have a phase difference corresponding to 1/2 the period, and so do the clock signals .phi.203 and .phi.204. The clock signals .phi.203 and .phi.204 go high when a predetermined time has elapsed after the clock signals .phi.201 and .phi.202 change to high level, respectively, and then simultaneously go low.
At transient time T200, assume that the node N201 is at 4 V (Vcc), the node N202 is at 0 V (GND), the node N203 is at about 5 V (Vpp), and the node N204 at 4 V (Vcc).
At time T201, since the clock signal .phi.201 goes high while the clock signal .phi.202 is at low level, the outputs from the driver DV201 and DV202 are at high and low levels, respectively. At this time, the transistors M1 and M3 are turned off, and the transistors M2 and M4 are turned on. Consequently, charges corresponding to 4 V which are stored on the node N201 side of the capacitor C201 move, through the transistors M2 and M4, to the node N202 side of the capacitor C202 which is being discharged to 0 V, so both the nodes N201 and N202 are set at 2 V (1/2.times.Vcc). On the other hand, charges corresponding to 5 V (Vpp) which are stored on the node N203 side of the capacitor C201 decrease by 2 V to 3 V (Vpp-1/2.times.Vcc). Charges corresponding to 2 V are added to the node N204 side of the capacitor C202 which is being charged to 4 V, so the node N204 is set at 6 V (3/2.times.Vcc).
At time T202, the clock signal .phi.203 goes high while the clock signal .phi.201 is at high level and the clock signal .phi.202 is at low level. The transistors M5 and M8 are turned on. As a result, the charges corresponding to 6 V (3/2.times.Vcc), which are stored on the node N204 side of the capacitor C202, are distributed to the load capacitor CL through the transistor M8, and the voltage converges to 5.5 V (Vpp). The node N203 side of the capacitor C201, which is being discharged to 3 V (Vpp-1/2.times.Vcc), is charged to 4 V, i.e., the power supply voltage Vcc through the transistor M5.
After this, the clocks .phi.201 and .phi.203 go low, and the transistors M2, M4, M5, and M8 are turned off. The voltage at each node is kept unchanged.
At time T203, the clock signal .phi.202 goes high, and the outputs from the drivers DV201 and DV202 are set at low and high levels, respectively. At this time, the transistors M1 and M3 are turned on, and the transistors M2 and M4 are turned off. The node N201 side of the capacitor C201 is charged to the power supply voltage Vcc of 4 V through the transistor M1. The node N202 side of the capacitor C202, which is being charged to 2 V, is set at GND, i.e., 0 V through the transistor M3.
On the node N203 side of the capacitor C201, which is being charged to 4 V, charges corresponding to 2 V are added to set the node N203 at 6 V (3/2.times.Vcc). On the node N204 side of the capacitor C202, which is being discharged to 5.5 V (Vpp), charges corresponding to 2 V are removed to set the node N204 at 3.5 V (Vpp-1/2.times.Vcc).
At time T204, the clock .phi.204 goes high while the clocks .phi.201 and .phi.202 are set at low and high levels, respectively, so the transistors M6 and M7 are turned on. As a result, charges corresponding to 6 V (3/2.times.Vcc), which are stored on the node N203 side of the capacitor C201, move to the load capacitor CL through the transistor M7 and the node NL, so the voltage converges to 5.75 V (Vpp). The node N204 side of the capacitor C202, which is being discharged to 3.5 V, is charged to the power supply voltage of 4 V through the transistor M6.
After this, the clocks .phi.202 and .phi.204 go low, and the transistors M1, M3, M6, and M7 are turned off. The voltage at each node is held.
By repeating this operation, the load capacitor CL is gradually charged to a higher voltage, and the output voltage Vpp finally converges to 6 V.
In the booster circuit of prior art 2, charges corresponding to the power supply voltage Vcc, which are stored in the capacitor C201, are distributed to the capacitor C202 through the transistors M2 and M4, and charges corresponding to 1/2.times.Vcc are stored in the capacitor C202. These charges are removed to the ground GND in response to the next clock. In this case, the loss charge amount for one period is C.times.Vcc/2 (coulomb). When Vcc is 4 V, the loss charge amount is 2C (coulomb). The loss charge amount per unit boost ratio is given by 1/3.times.C.times.Vcc (coulomb).
In the above-described booster circuit of prior art 1, the charge/discharge amount of the capacitor CP by switching is large, and charges corresponding to C.times.Vcc (coulomb) are lost per capacitor CP in one clock period. When four capacitors are arranged as in prior art 1, the loss becomes C.times.Vcc.times.4 (coulomb). This loss increases as the boost ratio of the booster circuit becomes high. Therefore, the power consumption of the circuit undesirably increases.
In the booster circuit of prior art 2, the pump circuit is connected to allow a bidirectional operation such that the boost operation is performed twice in one clock period, thereby increasing the current capacitance. In addition, since the transistors M2 and M4 are arranged, charges stored in the capacitor C201 are not grounded but used to charge the capacitor C202, and then the capacitor C202 is discharged. With this arrangement, the loss charge amount can be reduced, and consequently, the power consumption of the booster circuit can be decreased.
In the booster circuit of prior art 2, however, the voltage at the driving nodes N201 and N202 changes only by Vcc/2. Charges corresponding to only Vcc/2 can contribute to the boost operation, so no high voltage can be obtained. Therefore, the booster circuit of prior art 2 cannot be used for a write/erase in/from a flash memory because the voltage is too low, although it can be used as a write voltage for a memory cell of a DRAM.
In addition, the node N201 of the capacitor C201 must be switched between 0 V and 4 V by the transistors M1 and M2. The node N203 must be driven by the transistors M5 and M8 with a gate voltage of 2.times.Vcc, i.e., 8 V by using the capacitor C203 and the diode D201 to decrease the ON resistance of the transistors M5 and M8, and be switched at a voltage higher than the power supply voltage. In this circuit arrangement, the number of devices increases, resulting in a complex circuit arrangement.
Furthermore, prior art 2 does not disclose an arrangement for realizing a boost ratio of 3 or more. As one arrangement for realizing a boost ratio of 3 or more, a plurality of booster circuits of prior art 2 are prepared, and the output from an output terminal OUT of a preceding stage is supplied to the power supply terminal Vcc of the next stage. However, since the voltage becomes high toward the last stage, the breakdown voltage of a transistor M or diode D to be used must be increased. This increases the size of each device, although the number of devices per stage is large to already result in a large chip size.